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Figure 22 · Signal with Slowed Rate
To get adequate sample resolution, a good "rule of thumb" is to make sure the analyzer samples 4 to 10
times faster than the fastest signal being captured.
For example, if you wanted to capture a 40 nanosecond (ns) pulse, you would want the analyzer to sample
at least 4 times faster ( 40ns/4 = 10ns). Sampling 10 times faster may not be practical since it would require
an analyzer that samples every .4ns, or 2.5 giga-samples per second (GSa/s).
Capturing the entire signal
Logic analyzer sample buffers usually have a "fixed" size. This means that the faster memory is filled (the
faster the sample rate), the shorter the overall acquisition time will be.
If you need to capture a burst of data that lasts 5 ms. Let's also assume the sample buffer can store 64K
samples (actually 65536 samples since 64K is really 2^16). Simply divide 5ms by 65536 which results in
76.3 ns. In other words, with a 64K sample buffer and the analyzer sampling at 76 ns, it will capture 5 ms
worth of signal activity.
In reality the analyzer probably has fixed sample rate steps (such as 200 ns, 100 ns, 50 ns, 20 ns, etc.). To
comply with the requirements in the example above, we would not be able to sample faster than 76.3 ns and
still capture 5 ms worth of data. The closest alternative would be 100 ns, which would result in 6.6 ms worth
of data (65536 samples x 100 ns). Assuming 100 ns is fast enough to sample the input 4 times faster than
the fastest signal (100 ns * 4 = 400 ns pulse), we will meet our objectives for sample resolution and
acquisition length.
Sample Resolution
Sampling Resolution is the interval (in seconds) between samples, determined by the frequency of the
sample clock. Suppose, for example, that the sample clock was running at 100 MHz, and we were sampling
on the rising edge as shown below. The sample resolution would be 1/100 MHz, or 10 ns.
Figure 23 · Sample Resolution
When the timing analyzer samples an input line, it is either high or low. If the line is at one state (high or low)
on one sample and the opposite state on the next sample, the analyzer "knows" that the input signal
transitioned sometime in between the two samples. It doesn't know when, so it places the transition point at
the last sample, as shown below.
Figure 24 · Sample Uncertainty
This presents some uncertainty as to when the transition actually occurred and when it is displayed by the
analyzer. Worst case for this uncertainty is one sample period, assuming that the transition occurred
immediately after the previous sample point.
36
Silicon Explorer II User's Guide
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